The present invention relates in general to the field of mass storage devices, and more particularly to a system and method for enhancing a preamplifier read recovery when the mass storage device transitions from a non-read state to a read state.
Hard disk-drives such as the exemplary drive 10 illustrated in FIG. 1 include a stack of magnetically coated platters 12 that are used for storing information. The magnetically coated platters 12 are mounted together in a stacked position through a spindle 14 which may be referred to as a platter stack. The platter stack is typically rotated by a motor that is referred to as a spindle motor or a servo motor (not shown). A space is provided between each platter to allow an arm 18 having a read/write head or slider 20 associated therewith to be positioned on each side of each platter 12 so that information may be stored and retrieved. Information is stored on each side of each platter and is generally organized into sectors, tracks, zones, and cylinders.
Each of the read/write heads or sliders 20 are mounted to one end of the dedicated suspension arm 18 so that each of the read/write heads may be positioned as desired. The opposite end of each of the suspension arms 18 are coupled together at a voice coil motor 16 (VCM) to form one unit or assembly (often referred to as a head stack assembly) that is positionable by the voice coil motor. Each of the suspension arms 18 are provided in a fixed position relative to each other. The voice coil motor 16 positions all the suspension arms 18 so that the active read/write head 20 is properly positioned for reading or writing information. The read/write heads 20 may move from at least an inner diameter to an outer diameter of each platter 12 where data is stored. This distance may be referred to as a data stroke. Hard disk drives also include a variety of electronic circuitry for processing data and for controlling its overall operation. This electronic circuitry may include a pre-amplifier, a read channel, a write channel, a servo controller, a motor control circuit, a read-only memory (ROM), a random-access memory (RAM), and a variety of disk control circuitry (not shown) to control the operation of the hard disk drive and to properly interface the hard disk drive to a system bus. The pre-amplifier may contain a read pre-amplifier and a write pre-amplifier that is also referred to as a write driver. The pre-amplifier may be implemented in a single integrated circuit or in separate integrated circuits such as a read pre-amplifier and a write pre-amplifier or write driver. The disk control circuitry generally includes a separate microprocessor for executing instructions stored in memory to control the operation and interface of the hard disk drive.
Hard disk drives perform write, read, and servo operations when storing and retrieving data. Generally, a write operation includes receiving data from a system bus and storing the data in the RAM. The microprocessor schedules a series of events to allow the information to be transferred from the RAM to the platters 12 through the write channel. Before the information is transferred, the read/write heads 20 are positioned on the appropriate track and the appropriate sector of the track is located. The data from the RAM is then communicated to the write channel as a digital write signal. The write channel processes the digital write signal and generates an analog write signal. In doing this, the write channel may encode the data so that the data can be more reliably retrieved later. The digital write signal may then be provided to an appropriate read/write head 20 after first being conditioned by the pre-amplifier. Writing data to the recording medium or platter 12 is typically performed by applying a current to a coil of the head 20 so that a magnetic field is induced in an adjacent magnetically permeable core, with the core transmitting a magnetic signal across a spacing of the disk to magnetize a small pattern or digital bit of the media associated with the disk.
Circuitry associated with a read operation is illustrated in FIG. 2, and designated at reference numeral 30. In a read operation, the appropriate sector to be read is located and data that has been previously written to the platters 12 is read. The appropriate read/write head 20 (illustrated as a magneto-resistive load 20a in FIG. 2) senses the changes in the magnetic flux and generates a corresponding analog read signal. The analog read signal is provided back to the electronic circuitry where a preamplifier circuit 32 amplifies the analog read signal. The amplified analog read signal is then provided to a read channel circuit 34 where the read channel conditions the signal and detects xe2x80x9czerosxe2x80x9d and xe2x80x9conesxe2x80x9d from the signal to generate a digital read signal. The read channel may condition the signal by amplifying the signal to an appropriate level using, for example, automatic gain control (AGC) techniques. The read channel may then filter the signal to eliminate unwanted high frequency noise, equalize the channel, perform the data recovery from the signal, and format the digital read signal. The digital read signal is then transferred from the read channel and is stored in the RAM (not shown). The microprocessor may then communicate to the host that data is ready to be transferred.
The read channel circuit 34 may be implemented using any of a variety of known or available read channels. For example, the read channel 34 may be implemented as a peak detection type read channel or as a more advanced type of read channel utilizing discrete time signal processing. The peak detection type read channel involves level detecting the amplified analog read signal and determining if the waveform level is above a threshold level during a sampling window. The discrete time signal processing type read channel synchronously samples the amplified analog read signal using a data recovery clock. The sample is then processed through a series of mathematical manipulations using signal processing theory to generate the digital read signal. There are several types of discrete time signal processing read channels such as a partial response, maximum likelihood (PRML) channel; an extended PRML channel; an enhanced, extended PRML channel; a fixed delay tree search channel; and a decision feedback equalization channel.
As the disk platters 12 are rotating, the read/write heads 20 must align or remain on a particular track. This is accomplished by a servo operation through the use of a servo controller provided in a servo control loop. Referring to FIG. 3 which represents a plan view of an exemplary platter 12, in a servo operation a servo wedge 40 is read from a track 42 that generally includes track identification information and track misregistration information 44. The track misregistration information may also be referred to as position error information. The position error information 44 may be provided as servo bursts and may be used during both read and write operations to ensure that the read/write heads are properly aligned on a track. As a result of receiving the position error information, the servo controller generates a corresponding control signal to position the read/write heads 20 via the voice coil motor. The track identification information 44 from the servo wedge 40 is also used during read and write operations so that a track 42 may be properly identified.
Hard disk drive designers strive to provide higher capacity drives that operate at a high signal-to-noise ratio and a low bit error rate. To achieve higher capacities, the density of the data stored on each side of each platter must be increased. This places significant burdens on the hard disk drive electronic circuitry. For example, as the density increases, the magnetic transitions that are used to store data on the platters must be physically located more closely together. This often results in intersymbol interference when performing a read operation. As a result, the hard disk drive electronic circuitry must provide more sophisticated processing circuitry that operates at higher frequencies to accurately process the intersymbol interference and the higher frequency read signal. In some cases, the spindle motor speed is increased which further increases the frequency of the read signal and the write signal. Furthermore, the increase in density requires that the servo control system be provided with a higher bandwidth to increase the read/write head positioning resolution.
As discussed above, to account for the increased data storage density, the spindle motor speed is being increased from a platter rotational speed of about 5400 RPMs to about 7200 RPMs or greater. To account for the increased speed, the write-to-read transition timing for a head 20 becomes important. For example, when performing a write operation, the head 20 is traversing a track 42 on the platter 12 as the platter spins there beneath. As illustrated in FIG. 3, when a servo region or wedge 40 is encountered, the head 20 must quickly transition from a write state to a read state in order to read the servo information stored therein and then quickly transition back to a write state in order to continue writing the data to the platter 12. If the write-to-read transition timing is slow, then the servo wedge 40 must be larger since the platter is rotating at a generally constant speed. Since many servo wedges 40 exist on the platter 12 (e.g., about 60) an optimized write-to-read transition timing allows for the wedges 40 to be minimized, thereby increasing data storage density thereon.
In addition to the write-to-read transition timing being an important transition sequence, the increase in rotational speed of the platter has caused various other transition sequences that have heretofore been relatively unimportant (that is, designers did not give such sequencing a substantial amount of attention) to become a matter of greater design consideration. Such transition sequences involve a transition from a non-read state to a read state (often called a read recovery) and include, for example: an idle-to-read transition state, the bias current change-to-read state, the head change-to-read state, head change and bias current change-to-read state, and the bias current OFF/ON-to-read state. There is a need in the art to provide optimized state transition sequencing for high rotation platter speeds to provide high data storage density.
The present invention relates to a system and method of enhancing a read recovery of a hard disk drive preamplifier circuit when the system transitions from a non-read state to a read state. The invention improves the transition switching performance from a non-read state to a read state, saves chip area and reduces circuit complexity by providing a common sequencing for different state transitions to a read state.
According to one aspect of the present invention, a common transition switching methodology is employed whenever the disk drive transitions from a non-read state to a read state. The common transition switching methodology allows the same circuitry to be reused for each transition to a read state, thereby simplifying the control circuitry and saving die area which reduces cost. In the transition from a non-read state to a read state, a wait period is initiated once the unique non-read sequence is complete which advantageously minimizes noise or other adverse effects associated with the inductance associated with the preamplifier and the read channel.
After the predetermined wait period has expired, a pole associated with an AC coupler circuit between the preamplifier and the read channel circuit is shifted from a first, higher frequency to a second, lower frequency at a gradual predetermined rate, thus altering the band pass response of the AC coupler between non-read states and the read state. The gradual shifting of the pole slowly alters the phase of the preamplifier output signal as opposed to a generally instantaneous or fast shifting, thus avoiding read channel errors caused by the sampling of noise to the read channel circuit. After another predetermined period of time has passed in which the pole is gradually shifted, a squelch signal is de-asserted or otherwise transitions which removes a squelch condition such as a xe2x80x9cshort circuitxe2x80x9d condition across the preamplifier output so that the read function may be effectuated. Having the squelch condition activated during a non-read state prevents spurious noise from negatively impacting the signal processing circuitry.